Saqib, Fareena

Assistant Professor
Electrical and Computer Engineering

Educational Background

  • Doctor of Philosophy (Ph.D.) in Computer Engineering 2014, University of New Mexico, Albuquerque, NM, USA

          I received my Ph.D. in Electrical and Computer Engineering from University of New Mexico where I worked with Prof. Jim Plusquellic on Within-Die Delay Variation Measurement and Analysis for Emerging Technologies Using an Embedded Test Structure.

Recognition & Awards

  • Received a new grant from National Scence Foundation (NSF) for a project titled: HACE Lab: An Online Hardware Security Attack and Countermeasure Evaluation Lab
  • Received a new grant from National Science Foundation (NSF) for a project titled: Hardware based Authentication and Trusted Platform Module functions (HAT) for IoTs

          NSF Funded PhD position opening in Dr. Saqib's Group:

    • Applications are invited from motivated graduate students pursuing Ph.D. studies in Electrical and Computer Engineering at Florida Institute of Technology (FIT). The selected students will start working with me beginning Fall 2016 or Fall 2017. Ph.D. applicants must have a master degree in Computer Engineering/Electrical Engineering/ Computer Science or a closely related field. Successful candidates should have strong background in VLSI design, hardware security and trust, number theory, mathematical modeling and programming. Desirous students may check FIT webpage for information about the general application requirements of FIT and the Electrical and Computer Engineering Department. Interested graduate students can email me ( giving summary of their background and list of projects in the body of the email with a copy of CV in PDF format attached to it. Due to expected high volume of the incoming emails, I may be unable to respond to each of the applicants, but in case of good match I will definitely get back to such applicant(s). Thank you for your interest in Electrical and Computer Engineering.
  • Winner of Faculty Professional Development Award, Florida Institute of Technology 2015-2016
  • Proposal on “HELP-Hardware-Embedded Delay Physical Unclonable Function (PUF)” submitted to Comcast Center of Excellence for Hardware Assurance, Security and Engineering at University of Connecticut (UCONN) accepted as finalist for competition in CSI CyberSeed-Hardware Challenge being held in October, 2014
  • Recipient of University of New Mexico graduate-studies scholarship for PhD program 2011-2014
  • Recipient of University of New Mexico graduate-studies scholarship for MS program 2009 - 2010
  • Recipient of National University of Sciences & Technology (NUST) undergraduate merit scholarship 2002-2006
  • Awarded Fulbright Scholarship, 2008
  • Silver Medal in under graduate, 2006

Current Courses

ECE-5575 Hardware Oriented Security and Trust (Summer 2016, Spring 2017)

ECE-5575 Programmable Gate Arrays (FPGA) (Spring 2015, Spring 2016)

ECE-1551 Digital Logic (Fall 2015, Spring 2016, Fall 2016, Spring 2017)

ECE-5520 Advanced Computer Architecture (Fall 2015, Fall 2016)

 ECE-5570 Computer Architecture (Fall 2014)

Professional Experience

Fareena Saqib is an Assistant Professor at Florida Institute of Technology. She pursued her PhD Studies in Computer Engineering (2014) with specialization in Computer Architecture at the Department of Electrical and Computer Engineering, University of New Mexico (UNM); where she carried out research on “Within-die variation measurement and analysis using an embedded test structure REBEL in ASIC and FPGAs”. Also conducted research on “Pipelined decision tree classification accelerator implementation in FPGAs”. Prior to that, she earned her M.S. degree in Computer Engineering (2010) from UNM with research emphasis on “Enhanced crankback signaling for multi-domain IP/MPLS networks using standard RSVP-TE protocol”; and Bachelor’s degree in Information Technology (2006) from NUST with research focused on “Network weather forecasting for management and analysis of global grid and internet end to end performance (MAGGIE) using ARMA/ARIMA time series”.

She has varied experience in industry, consultancy services as well as teaching and research. Also, she has applied-research experience in the use of quantitative models and information technology for improving efficiency and effectiveness of operations in the telecommunication industry and business.

Additional Duties

Currently serving as a reviewer for several IEEE professional journals/publications including Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Transaction on Information Forensic Security (TIFS), Transactions on Circuits and Systems (TCAS), Transactions on Computers (TC), Transactions on Emerging Technologies in Computing (TETS) and International Symposium on Hardware-Oriented Security and Trust (HOST).

Served as NSF Panelist (2015)

Serving as Faculty Advisor for Students Chapter of IEEE at Florida Tech (2015-2016)

Selected Publications

1) Fareena Saqib, Jim Plusquellic, Book Chapter-2 “VLSI Test and Hardware Security Background for Hardware Obfuscation” pp 33-68 in D. Forte, S. Bhunia, M. Tehranipoor (Eds), Hardware Protection through Obfuscation, Springer International Publishing 2017, 347 pp.

2) Wenjie Che, Mitchell Martin, Goutham Pocklassery, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic, “A Privacy-Preserving, Mutual PUF-Based Authentication Protocol”, Cryptography, 2017, Vol. 1, Issue 1, pp. 1-17.

3) Fareena Saqib, Jim Plusquellic, Al Faroaque, “Hardware Security and Trust Challenges in Emerging IoT Systems and Applications” (Toturial), HOST 2017.

4) William Arrasmith, Barry Webster, Fareena Saqib, “Software dominant unconventional optical imaging through atmospheric turbulence with advances towards real-time, diffraction-limited performance”, In-Tech 2016 International Conference on Innovative Technologies held in Prague, Czech Republic during 6-8 September 2016.

5) Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib, “On detecting delay anomalies introduced by hardware trojans”, ICCAD '16: Proceedings of the 35th International Conference on Computer-Aided Design, Austin, TX, USA, November 2016, 7 pp.

6) Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib, “Hardware Based Security Enhanced Framework for Automotives”, 2016 IEEE Vehicular Networking Conference (VNC), December 2016, Columbus, OH, USA.

7) W. Che, F. Saqib, J. Plusquellic, “PUF-Based Authentication”, Invited Paper, International Conference on Computer-Aided Design (ICCAD), 2-6 Nov. 2015.

8) D. Ismari, C. Lamech, Swarup Bhunia, F. Saqib, and J. Plusquellic, Detecting Delay Anomalies Introduced by Hardware Trojans using Chip-Averaging and an On-Chip High Resolution Embedded Test Structure, 2015.

9) I. Wilcox, F. Saqib, and J. Plusquellic, GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units, HOST, May., 2015.

10) C. Konstantinou, M. Maniatakos, F. Saqib, Shiyan Hu, J. Plusquellic, Yier Jin, Cyber-Physical Systems: A Security Perspective, European Test Symposium (ETS), 25-29 May 2015, pp. 1-8.

11) F. Saqib, J. Plusquellic “An ASIC Implementation of Hardware based PUFs using Path delays as source of entropy ” SaTC Principal Investigators’ Meeting organized by U.S. National Science Foundation (NSF) under its Secure and Trustworthy Cyberspace (SaTC) program held in Arlington VA, at the Hyatt Regency Crystal City, January 5-7, 2015.

12) F. Saqib, M. Areno, J. Aarestad, J. Plusquellic, “An ASIC implementation of a hardware-embedded physical unclonable function”, IET Computers and Digital Techniques, Vol 8, Issue 6, Nov. 2014, pp 288-299.

13) F. Saqib, D. Ismari and J. Plusquellic, “Within-Die Delay Variation Measurement and Analysis Using An Embedded Test Structure”, IEEETrans. on VLSI, Vol. PP, Issue 99, May, 2014.

14) F. Saqib, and J. Plusquellic, “Design for manufacturability for yield improvement by using embedded test structures”, NanoFlorida, Miami, Florida, September 2014.

15) F. Saqib, A. Dutta, J. Plusquellic, P. Ortiz, M. S. Pattichis, “Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)”, accepted to IEEE Trans. on Computers, Volume: PP , Issue: 99, pp. 1, Oct. 2013.


16) F. Saqib, Within-die delay variation measurement and analysis for emerging technologies using an embedded test structure, PhD Dissertation, Department of Electrical and Computer Engineering, University of New Mexico (UNM), 2014 (Advisor: Dr. Jim Plusquellic)

– available at University of New Mexico USA web page:

17) F. Saqib, Enhanced crankback signaling for multi-domain IP/MPLS networks using standard RSVPTE protocol, Master’s Thesis, Department of Electrical and Computer Engineering, University of New Mexico (UNM), 2010 (Advisor: Dr. Nasir Ghani)

– available at University of New Mexico USA webpage:

18) F. Saqib, Network weather forecasting for management and analysis of global grid and internet end to end performance (MAGGI), Bachelor’s Thesis, National University of Sciences and Technology (NUST), Pakistan, 2006 (Advisor: Dr. Arshad Ali, Dr. Les Cottrell and Umar Kalim)

– available at Stanford Linear Accelerator Center (SLAC) of Stanford University USA web page:

Invited Talks, seminars

“Within-Die Delay Variation Measurement and Analysis using Embedded Test Structure”, Invited Talk in ECE Graduate Seminars Series, University of New Mexico, October 2013.
“Cultivating Curiosity in Electrical and Computer Engineering and Exploring Areas of Interest for High School Students”, under Mentorship Program at ECE, University of New Mexico, November 2013.